System and method to improve switching in power switching applications

ABSTRACT

A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which the or each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal

FIELD OF THE INVENTION

This invention relates to a product, system, method and computer programto improve switching in power switching applications and moreparticularly to manage time delays of power up and power down processes.

BACKGROUND OF THE INVENTION

Pulse width modulation (PWM) is a technology which modulates anelectronic signal or a power source in order to transmit information toan electronic device or to control the amount of power sent to anelectronic device. PWM occurs in many applications such as powerlighting applications for example.

With PWM technology the amount of power sent to a light device such as aLight Emitting Diode (LED), through a switch such as a MOS powertransistor or MOSFET (Metal Oxide Semiconductor Field EffectTransistor), can be controlled. The use of PWM technology with low dutycycles requires that the time delay for switching on the MOSFET and thecorresponding time delay for switching off the MOSFET are nearlysymmetrical. The aim is to ensure that the ON time of the input controlsignal of the MOSFET equals the ON time of the output voltage of theMOSFET. Thus, the MOSFET can run with low duty cycle. Therefore, thepower of the LED is modulated and the lifetime of the LED is greatlyenhanced. However, the MOSFET takes generally more time to switch offthan to switch on. The unsymmetrical time delays for switching on andoff the MOSFET come from the manufacturing process and dynamiccharacteristics of MOSFET technology.

Indeed the manufacturing process gives rise to mistakes caused byetching and metallization process for example. With these, there is noguarantee that each integrated circuit will have exactly samecharacteristics for each component thereon. This difference in behaviourof various components of the MOSFET leads further additional time delaybetween the switching off and switching on processes of a lightingdevice such as an LED.

US 2003/201811 discloses a method and device for symmetrical slew ratecalibration. The aim of US2003/201811 is to directly measure slew ratesfor push pull driver devices in order to calibrate slew rates. Themethod uses a driver acting as an oscillator.

U.S. Pat. No. 7,133,790 discloses a method and system of calibrating acontrol delay time. The method uses a comparison step which uses apredefined pattern.

SUMMARY OF THE INVENTION

The present invention provides a product, system, method and computerprogram for controlling the time delay between a switch ON and twoswitch OFF signals as described in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made, by way of example, to the accompanyingdrawings, in which:

FIG. 1 is a representation of an electronic circuit in accordance with afirst example of an embodiment of the invention, given by way ofexample,

FIG. 2 is a graph of electronic signals versus time in accordance withan embodiment of the invention, given by way of example,

FIG. 3 is a flow chart of a first example of a method in accordance withthe invention, given by way of example,

FIG. 4 is a representation of an electronic circuit in accordance with asecond example of an embodiment of the invention, given by way ofexample,

FIG. 5 is a graph of electronic signals versus time in accordance withan embodiment of the invention, given by way of example and

FIG. 6 is a flow chart of a second example of a method in accordancewith the invention, given by way of example,

FIG. 7 is a representation of a lighting circuit in accordance with anembodiment of the invention, given by way of example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 shows a representation of a circuit 100. The circuit100 is a part of a LED driver circuit. The circuit 100 comprises acomparator 102, which in this example includes an operational amplifier(OA) which is used as a comparator. The OA has a power supply Vbat of abattery 101. Vbat generally equals 12 to 14 volts (V). A control module103 controls the power switching of a MOSFET 104 (Metal OxideSemiconductor Field Effect Transistor) 104 through an input control ONsignal i.e. an ON instruction for the switching ON state of the MOSFET104 and an input control OFF signal i.e. an OFF instruction for theswitching OFF state of the MOSFET 104. Vsource is the source voltage ofthe MOSFET 104. MOSFET 104 comprises a drain D, a gate G and a source S.Vsource can be a switching OFF signal, a switching ON signal or arunning state signal as will be defined below. When the control module103 has an ON instruction, the MOSFET 104 is about to be switched ON andconsequently the LED (not shown) will be switched ON. When the controlmodule 103 has an OFF instruction, the MOSFET 104 is about to beswitched OFF and consequently the LED (not shown) will be switched OFF.The comparator 102 has a non-inverting input voltage V1 called Vgate.Vgate refers to the voltage of the gate of the MOSFET 104, relative tothe ground. Vgate varies depending from the change in state ON or OFF ofthe MOSFET 104. When the MOSFET 104 is switched ON, Vgate increases from0V to Vbat+12V and when the MOSFET 104 is switched OFF, Vgate increasesfrom Vbat+12V to 0V. The value of 12V is just an example and may bedifferent according to the voltage required for the gate, between 10 and12 V for example. A second inverting input voltage V2 equals to Vbat+3V.

This value of V2 is a threshold value defined experimentally asdescribed below. The value of 3V is just an example. The value of 3Vdepends on the technical characteristic of the electronic components ofthe MOSFET 104. Therefore, the value of 3V may be different according tothe MOSFET 104 used for determining the threshold value V2. Voutcomp isthe output voltage of the OA. Voutcomp results from a comparison betweenV1 and V2 as the OA is used as a comparator 102 as mentioned above.Voutcomp is so defined that Voutcomp is at a high level when V1 is lowerthan V2 and the reference voltage of the OA is V2. In the first presentembodiment the gate of the MOSFET 104 is used as V1 and the drain D ofthe MOSFET 104 is used as Vbat. The source of the MOSFET is directlyconnected to a load 113. The load 113 is directly connected to theground. Indeed, it appears after several tests on specific powerswitches that the change of the voltage value of Vgate from the maximumvalue of Vbat+12V to the value of V2 indicates that the MOSFET 104 isbeing switched off. When Vgate decreases to V2, the time of thedecreasing refers to a time Tdetoff, which will be used to define thesymmetry between TdelayON and TdelayOFF as described below. Thus, theMOSFET 104 is defined with three states, which are a switching ON state,a switching OFF state and a running state. The signal of Vsource canrepresent either a switching OFF signal, a switching ON signal or arunning signal. The switching ON and OFF states respectively define aswitch ON delay which is TdelayON and a switch OFF delay which isTdelayOFF.

The circuit 100 also comprises different modules, which are connected tothe comparator 102. The modules are a load module 106, a counter 108, anOFF registering module 110 and a comparison module 112. Thus, thecomparator 102 is communicatively connected to the load module 106. Theload module 106 is connected to the OFF registering module 110. The loadmodule 106 is also connected to the counter 108. The counter 108connects both the OFF registering module and the comparison module 112.The OFF registering module 110 is connected to the comparison module112. The comparison module 112 is connected to the control module 103which connects the MOFSET 104. The MOSFET 104 is directly connected tothe comparator 102. The counter 108 and the OFF registering module 110represent determining unit. The comparator 102 represents a calculator.The load module 106 monitors the signal Voutcomp to send the content ofthe counter 108 to an ON register 302 and/or an OFF register 110 asshown in FIG. 3. The counter 108 measures the time during which thesignal Voutcomp from the comparator 102 is high, starting from thecontrol module 103 sending an OFF instruction. This unit that thecounter 108 only measures the time delays TdelayON, TdelayOFF when Vgateis higher than V2. The OFF registering module 110 specifically registersthe time values of TdetOFF for switching OFF signals during severalswitching OFF states. FIG. 2 shows an example of a TdetOFF measuredduring a switching OFF state signal occurring when the control module103 has an OFF instruction. TdetOFF results from the measured time forVgate to decrease from a high level i.e. Vgate to a low level i.e. V2.As the comparison module 112 is connected to the counter 108, thecomparison module 112 monitors the time lag being added to a switchingON state signal. As the comparison module 112 is also connected to theOFF registering module 110, the comparison module 112 compares the timelag being added to the switching ON state signal with the registeredTdetOFF in the OFF registering module 110. The comparison process occursin order to add to the switching ON state signal a time lag. The timelag added to the switching ON state signal is the same as the registeredvalue in the OFF registering module 110.

The circuit 100 shown in FIG. 1 may execute an example of a method forcontrolling a change in state of a signal. The method will now bedescribed with reference to the steps as shown in FIG. 3. The processbegins with the control module 103 having an OFF instruction. This unitthat the MOSFET 104 is about to be switched OFF and that Vsourcecorresponds to a switching OFF state signal. Then Vgate decreases fromVbat+12V to 0V. In a step 200, the counter 108 starts to increment whilethe load module monitors the falling edge of the signal Voutcomp. In astep 202, the counter 108 begins to measure a specific time called theTdetoff relating to Voutcomp. Tdetoff represents the useful time for theMOSFET 104 to go from saturation to a linear response.

In the saturation state, the MOSFET 104 is driven as a switch (a verylow drain to source on resistance rds on with the gate 12 V higher thanthe source, that is the gate source voltage Vgs=12V. This Vgs valuecould be different depending from the power switches concerned by themethod. The Vgs value may vary from 10 to 12 V for example. In thelinear state, the MOSFET 104 is driven as a resistance. From thesaturation to linear states the Voutcomp signal is high. In a step 204,as soon as Vgate reaches the defined value Vbat+3V, the counter 108stops measuring time and Vsource continues to decrease to 0. Thus, in astep 206, the registering module 106 records the specific measured valueof Tdetoff. Then the process follows with an ON instruction from thecontrol module 103. This unit that the MOSFET 104 is about to beswitched ON, and that Vsource corresponds to a switching ON state signalhaving a TdelayON to switch ON the MOSFET 104. In a step 208 the counter108 begins to run in order to add a time lag to the input control ONsignal before switching ON the MOSFET 104. The time lag refers to theTdetoff already registered in step 206. The time lag is a voluntarydigital added delay and does not result from dynamic characteristics ofelectronic components which also may produce a time lag. Therefore,before switching ON the MOSFET 104, the consign “input control ON” isdelayed during a time, which equals Tdetoff as mentioned above. Duringthe process of adding the time lag to TdelayON, in step 210, thecomparison module 112 regularly checks that the added time lag does notexceed the value of Tdetoff registered in the registering module 106. Assoon as the time lag equals Tdetoff registered in the previous switchingOFF state, the comparison module 112 allows the MOSFET 104 to beswitched ON in a step 212. Thus, Vgate increases from 0 to Vbat+12V.Then following the process, the control module 103 has an OFFinstruction. Thus, the MOSFET 104 is about to be switched OFF andVsource now refers to a switching OFF state signal. In the presentembodiment, no time lag is added to the switching OFF state signal,therefore the LED (not shown) is being switched OFF without anyadditional time lag. The counter 108 runs in order to measures a newTdetoff relating to the time it takes for the MOSFET 104 to be switchedOFF. As previously mentioned, as soon as Vgate reaches the value ofVbat+3V, when decreasing to 0, the counter 108 stops measuring Tdetoff.Then the new value of Tdetoff is registered in the registering module106. When the control module 103 has an ON instruction, Vsource refersto a switching ON state signal. Then, the counter 108 begins to run inorder to add a time lag to the consign “input control ON”. Thecomparison module 112 checks that the time lag reaches exactly the newvalue of Tdetoff registered in the registering module. As soon as thetime lag reaches the new value of Tdetoff, the counter 108 stops and thecomparison module 112 allows the Power MOSFET 104 to be switched ON. Theprocess may repeat the above-mentioned steps as required by switchingthe MOSFET 104 off and on.

In the present embodiment of the invention, the time delay between thepoint in time the input control OFF signal is provided and the MOSFET104 is really switched OFF is not adjusted and the time delay betweenthe point in time the input control ON signal is provide and the MOSFET104 is really switched ON is adjusted with a defined time lag. The timelag of a current switch ON signal is based on Tdetoff previous switchOFF signal. Therefore, the total current time delay of a current switchON signal equals the current time delay of the switch ON signal plus theprevious Tdetoff delay of the switch OFF signal, which unit that thecorrected TdelayON is the sum of the TdelayON and Tdetoff. Thus, if theTdelayON equals to 10 μs and Tdetoff equals to 20 μs, the addition ofthe time lag, 20 μs, provides a corrected value of TdelayON, whichequals 30 μs. As the process repeats, the next value of the correctedTdelayON follows the variations of Tdetoff.

FIG. 4 shows a second embodiment of the invention with a circuit 100 a.In FIGS. 1 and 4, the same reference signs indicate like elements, andfor sake of brevity those elements are not described again. As shown inFIG. 4, in addition to the elements of FIG. 1, FIG. 4 shows anadditional ON registering module 302 and a calculation module 304. TheON registering module 302, as the OFF registering module 110, representsa determining unit in addition to the above cited determining unit andthe calculation module 304 represents a calculator in addition to theabove cited calculator. The ON registering module 302 registers thevalue of TdelayON of the switching ON state signal. Therefore, bothTdelayON and TdelayOFF are registered in their corresponding ON and OFFregistering modules 110. The ON registering module 302 and the OFFregistering module 110 may also be gathered in a same module withdifferent parts. The calculation module 304 calculates the subtractionbetween TdelayON and TdelayOFF. The result of the subtraction is acorrected time lag. The calculation module 304 further indicates whichone of the time delays TdelayON and TdelayOFF has the largest value. Thecalculation module 304 and the counter 108 both connect OFF registeringmodule 110 and ON registering module 302 and also connect in additioncomparison module 112. The OFF registering module 110 and the ONregistering module 302 are connected with the calculation module 304.The calculation module 304 is connected to the comparison module 112.

The calculation module 304 outputs the result of the subtraction and theindication to the comparison module 112. With the output of thecalculation module 304, the comparison module 112 is able to determinewhich one of the time delays TdelayON and TdelayOFF is the greatest andconsequently which signal has to be delayed to optimise operation.Differing from the first embodiment as shown in FIG. 5, the thresholdvalue for the change of switch ON and switch OFF state for the secondembodiment is Vbat/2 while V1 equals the source voltage of Power MOSFET104 (i.e. Vsource). In order to measure a time, for an electronicdevice, for switching OFF or for switching ON, the switch ON or switchOFF signal is measured at 50% of the total amplitude of the switch ON orswitch OFF signal. Thus, as the total amplitude in the presentembodiment is Vbat, therefore the time for switching ON or switching OFFis 50% of Vbat i.e. Vbat/2. The advantage of such a threshold valueVbat/2 is that Vbat/2 varies according to the change of the battery. Infact, when the control module 103 has an OFF instruction, meaning theMOSFET 104 is about to be switched OFF such that when the source voltageVsource reaches the threshold value Vbat/2, the MOSFET 104 is consideredas being switched OFF which unit that the MOSFET 104 is not alreadyswitched OFF. FIG. 5 shows an example of a TdelayOFF and a TdelayONmeasured during a switching OFF and a switching ON state signalrespectively when the control module 103 has an OFF instruction and anON instruction.

The circuit 100 shown in FIG. 4 may execute an example of a method forcontrolling a change in state of a signal, as will now be described withreference to the steps shown in FIG. 6. In this second embodiment, thesource is used as V1 and the drain is connected to the ground. Theprocess begins with the control module 103 having an ON instruction.This unit that the MOSFET is about to be switched ON and that Vsourcerefers to a switch ON state signal. Then Vgate increases from 0 toVbat+12V. In a step 602, the load module 106 sends the content of thecounter to the ON register on the rising edge of Voutcomp. In a step604, the counter 108 begins to measure TdelayON, which corresponds tothe time value for Vsource to reach Vbat/2. As the process of thecircuit may generate some modifications in the characteristics of thecomponents, a default value is added to the consign “input control ON”at the beginning of the process. This default value can be for example 4μs. Thus, the counter 108 begins by measuring the default value. Thenthe counter 108 additionally measures TdelayON; Tdelay ON can be forexample 15 μs. As soon as Vsource reaches Vbat/2, the value of totalTdelayON which equals the default value plus TdelayON, i.e. 19 μs, isregistered in the ON registering module 302 and the counter 108 stopsmeasuring TdelayON as in step 604. Thus, during this ON instructionperiod, the total TdelayON has a value of 19 μs, which is the additionof the default value and TdelayON. Then, the control module 103 has anOFF instruction. This unit that Voutcomp now refers to a switch OFFstate signal. In a step 608, the load module sends the content of thecounter 108 to the OFF register on the falling edge of Voutcomp. In astep 610, the counter 108 measures TdelayOFF, which corresponds to thetime for Vsource to go from Vbat/2 to 0V. As soon as Vsource reachesVbat/2, the counter 108 stops measuring TdelayOFF in a step 612 and thevalue of TdelayOFF, for example 20 μs, is registered in the OFFregistering module 110 in a step 614. Thus, during this OFF instructionperiod, TdelayOFF has a value of 20 μs. Then, in a step 616, thecalculation module 304 is able to calculate the difference betweenTdelayON and TdelayOFF, i.e. 19−20=−1 μs. Thus, the calculation module304 gives the value of the time lag, i.e. 1 μs between the switch OFFstate signal and the switch ON state signal and, with the sign (i.e.positive or negative) of the result, the calculation module 304determines which time delay is the highest, i.e. TdelayOFF. Thus, instep 618, the comparator can determine which signal needs to be delayedwith the time lag indicated in the calculation module 304. Then thecontrol module 103 has an ON instruction. Thus, Vgate will go from 0 toVbat+12V. Before switching ON the MOSFET 104, in a step 620 thecomparator launches the counter 108 in order to delay the switching ONsignal with the value of the time lag indicated in the calculationmodule 304. Thus, the switching ON state is not set until the time lagindicated in the OFF registering module 110 has finished. In a step 622,the comparison module 112 has to check the counter 108 in order to stopthe counter 108 when it reaches the value of the time lag. As soon asthe counter 108 reaches the value of the time lag, the comparison module112 allows the switch ON state and the counter 108 continues to measurethe TdelayON in a step 626. As soon as Vsource reaches Vbat/2, thecounter 108 stops measuring TdelayON in a step 628 and registers thevalue of TdelayON in the ON registering module 302 in a step 630.Therefore, the counter 108 registers time lag plus TdelayON, i.e. 1μs+19 μs. Thus, the total TdelayON during this ON instruction is 20 μs.Therefore, TdelayON has the same value as TdelayOFF above-mentioned,which is 20 μs.

In the present embodiment of the invention, it is preferred that thetime delay to switch OFF substantially equals the time delay to switchON. The time lag of the delayed switch signal corresponds to the maximumvalue between TdelayON and TdelayOFF. The chosen example has apredetermined TdelayOFF higher than TdelayON. Thus, TdelayON is delayedto come to a corrected TdelayON, which equals TdelayOFF.

In the situation where TdelayON is higher than TdelayOFF, the delayingprocess delays TdelayOFF in order to provide a corrected TdelayON, whichequals the value of TdelayON.

FIG. 7 shows a global diagram 700 of a lighting circuit in a car forexample. The diagram includes a device 702 in accordance with thepresent invention. The diagram represents four parallel connectionscomprising circuit inputs IN1, IN2, IN3 and IN4. Thus, in the diagram700, the device 702 drives the output of four MOSFET 104 as will bedescribed below. Each circuit input IN1, IN2, IN3 and IN4 relates to aspecific lighting application in the car such as brake lights, indicatorlights, etc. The circuit may comprise more or less than four circuitinputs. Different control signals (not shown) control the activation ofeach circuit input such as for example, the turn of a key when startingthe engine. Each circuit input has a defined corresponding input IN1,IN2, IN3 and IN4 in the device 702. Inputs IN1, IN2, IN3 and IN4 stillrefer to a specific lighting application in the car as mentioned above.Inputs IN1, IN2, IN3 and IN4 refer to different signals which are sentto the gate of the MOSFET 104 of the device 702 after a signal process(not shown). Inputs IN1, IN2, IN3 and IN4 also have correspondingoutputs OUT1, OUT2, OUT3 and OUT4 which refer to Vsource as defined inthe description. Outside the device 702, each output signal enters anLED 704, which is serially connected to one output on each line. FIG. 7shows three LEDs 704 per line as an example. Each connection may haveone or more LEDs 704 and each connection may have a different number ofLEDs than another connection. Additionally, the diagram 700 shows apulse width modulation clock PWM CLK connected to the device 702. ThePWM CLK gives the frequency of the signal in order to determine the PWMsampling frequency for the entering signals of the device 702.

The present invention allows the MOSFET 104 to work in many kinds ofduty cycles which unit that the MOSFET 104 can work for any kind ofratio of run time to total cycle of time. More specifically for thedisclosed embodiments, the MOSFET 104 works efficiently in a high dutycycle such as between about 95% and 100% and also in low duty cycle suchas between about 0% and 5%.

In the foregoing specification, the invention has been described withreference to specific examples of embodiments of the invention. It will,however, be evident that various modifications and changes may be madetherein without departing from the broader spirit and scope of theinvention as set forth in the appended claims. For example, theconnections may be a type of connection suitable to transfer signalsfrom or to the respective nodes, units or devices, for example viaintermediate devices. Accordingly, unless implied or stated otherwisethe connections may for example be direct connections or indirectconnections.

It will be appreciated that the examples described above relate tolighting applications. Other alternatives may exist for MOSFETS 104 usedfor any other applications such as motor applications for example, whichfall within the scope of the present invention.

Also, for example, the invention may be used for soft start on a motorcontrol for a window and the like.

Also, the invention is not limited to physical devices or unitsimplemented in non-programmable hardware but can also be applied inprogrammable devices or units able to perform the desired devicefunctions by operating in accordance with suitable program code.Furthermore, the devices may be physically distributed over a number ofapparatus, while functionally operating as a single device.

For example, the invention may be used for domestic applications such asmotorized shutters and the like.

Also, devices functionally forming separate devices may be integrated ina single physical device. For example, the circuit of the invention maybe associated within a micro controller.

However, other modifications, variations and alternatives are alsopossible. The specifications and drawings are, accordingly, to beregarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. The word “comprising” does notexclude the presence of other elements or steps then those listed in aclaim. Furthermore, the words ‘a’ and ‘an’ shall not be construed aslimited to ‘only one’, but instead are used to mean ‘at least one’, anddo not exclude a plurality. The mere fact that certain measures arerecited in mutually different claims does not indicate that acombination of these measures cannot be used to advantage.

1. A circuit for controlling of a change in state of a signal in anelectronic device between a first OFF state and a second ON state,wherein a first change in state occurs when the state changes from thesecond ON state to the first OFF state and a second change in stateoccurs when the state changes from the first OFF state to the second ONstate and wherein the first change in state has associated therewith afirst time delay over which the first change in state occurs, thecircuit comprises: a control unit for applying an instruction to theelectronic device for triggering the change in state; a determining unitfor measuring the first time delay; and a calculator for calculating atime lag based on the first delay and delaying the triggering of thesecond change in state by the time lag.
 2. A circuit as claimed in claim1, wherein the calculator compares a characteristic voltage of theelectronic device and a predetermined threshold value to determine thefirst time delay.
 3. A circuit as claimed in claim 1 wherein the secondchange in state has associated therewith a second time delay over whichthe second change in state occurs, and the determining unit furthermeasures the second time delay; and the calculator for calculating thetime lag based on a difference between the first time delay and thesecond time delay and determining either the first or the second timedelay as a shortest time delay and delaying the triggering of the secondchange in state by the time lag when the first time delay is theshortest delay and delaying the triggering of the first change in stateby the time lag when the second time delay is the shortest delay.
 4. Acircuit as claimed in claim 1, wherein the first change in statecomprises a saturation phase and the first time delay corresponds to aduration of the saturation phase.
 5. A circuit as claimed in claim 1,wherein determining unit measures the first time delay when theelectronic device is switched OFF.
 6. A circuit as claimed in claim 4,wherein determining unit measures the first time delay when theelectronic device is switched ON.
 7. A circuit as claimed in claim 1,wherein the circuit operates in a high duty cycle such as between about95% and 100%.
 8. A circuit as claimed in claim 1, wherein the circuitoperates in a low duty cycle such as between about 0% and 5%.
 9. Asystem for controlling the change in state of an electronic deviceincluding a circuit according to any of claims
 1. 10. A system asclaimed in claim 9, further comprising an electronic device.
 11. Asystem as claimed in claim 9 for controlling the switching of a lightingdevice, such as an LED.
 12. A method for controlling a change in stateof a signal in an electronic device between a first OFF state and asecond ON state, wherein a first change in state occurs when the statechanges from the second ON state to the first OFF state and a secondchange in state occurs when the state changes from the first OFF stateto the second ON state and wherein the first change in state hasassociated therewith a first time delay over which the first change instate occurs, said method comprises the following steps: determining thefirst time delay associated with the first change in state; calculatinga time lag based on the first delay and delaying a triggering of thesecond change in state by the time lag.
 13. A method as claimed in claim12, further comprising determining a second time delay associated withthe second change in state; calculating the time lag based on adifference between the first time delay and the second time delay anddetermining either the first or the second time delay as a shortestdelay; delaying the triggering of the second change in state by the timelag when the first time delay is the shortest delay and delaying thetriggering of the first change in state by the time lag when the secondtime delay is the shortest delay.
 14. A method as claimed in claim 12,further comprising running the electronic device in a high duty cyclesuch as between about 95% and 100%.
 15. A method as claimed in claim 12,further comprising running the electronic device in a low duty cyclesuch as between about 0% and 5%.
 16. (canceled)
 17. A method as claimedin claim 13, further comprising running the electronic device in a highduty cycle such as between about 95% and 100%.
 18. A method as claimedin claim 14, further comprising running the electronic device in a lowduty cycle such as between about 0% and 5%.
 19. A circuit as claimed inclaim 2 wherein the second change in state has associated therewith asecond time delay over which the second change in state occurs, and thedetermining unit further measures the second time delay; and thecalculator for calculating the time lag based on a difference betweenthe first time delay and the second time delay and determining eitherthe first or the second time delay as a shortest time delay and delayingthe triggering of the second change in state by the time lag when thefirst time delay is the shortest delay and delaying the triggering ofthe first change in state by the time lag when the second time delay isthe shortest delay.
 20. A circuit as claimed in claim 7 wherein thecircuit operates in a low duty cycle such as between about 0% and 5%.21. A computer readable medium including a computer program comprisinginstructions that when executed on a computer, carry out a method forcontrolling a change in state of a signal in an electronic devicebetween a first OFF state and a second ON state, wherein a first changein state occurs when the state changes from the second ON state to thefirst OFF state and a second change in state occurs when the statechanges from the first OFF state to the second ON state and wherein thefirst change in state has associated therewith a first time delay overwhich the first change in state occurs, said method comprises thefollowing steps: determining the first time delay associated with thefirst change in state; calculating a time lag based on the first delayand delaying a triggering of the second change in state by the time lag.